[Source: CSR]

Description

SiRFstarIV GSD4t is the first generation of the SiRFstarIV architecture. Optimised for size-constrained applications, it uses a host CPU to run the navigation libraries. Product manufacturers benefit from significant power consumption improvements, small package size, ease of integration and low-cost implementation.

A GSD4t solution comprises a GSD4t hardware implementation with SiRFHost™ software running on a host CPU. GSD4t includes an internal satellite signal tracking engine to provide highly accurate GPS measurements. Data buffering and queuing eliminates the need for a high-rate GPS interrupt, allowing the GSD4t Host Interface to run at low clock speeds with a very small host memory footprint.

Key features

  • High-performance solution
  • Low power
  • Low-risk, high-flexibility software
  • Tiny solution size
  • Simple to use
  • Fast, responsive location experience
  • High speed location engine
  • 48 channels available for acquisition
  • More than double the memory and more than double the clock speed of SiRFstarIII™
  • Active transmit blanking

Benefits

Breakthrough Power Consumption

  • Adaptive micropower controller
  • SiRFaware™ maintains hot-start readiness with only 150 to 500μA current for capture/update
  • Eliminates the need to turn off GPS receiver
  • 8 milliwatts TricklePower consumption

Reliable Choice For Difficult Environments

  • Active jammer remover
  • Tracks up to 8 CW jammers
  • Removes in-band jammers up to 80dB-Hz
  • 6 to 8dB of 3GPP design margin

Enhanced Navigation

  • Smart sensor interface
  • Multi-master I²C bus for smart sensors interrupt

GSD4t Hardware Description

The GSD4t product is designed for wireless handset applications. By minimising the external BOM to a single SAW and 4 to 9 passives, and the chip package to a 42-ball WLCSP, impact to end product size is minimal. Further enhancements to the silicon support simple design-in and low engineering risks:

  • Active Jamming Removal: The GSD4t device can track and remove energy from up to 8 separate CW jammers. Since this feature is integrated into the device, no prior knowledge of the jamming signal is required. This feature can be used in the design stage, in production to overcome last-minute issues with unexpected jamming, and during operation to eliminate « in the field » jamming.
  • High Performance Measurement Engine: The GSD4t core measurement engine contains more than double the memory of SiRFstarIII and operates at more than double the clock speed. It also supports shared VC-TCXO operation and self contained active transmit blanking.
  • Adaptive Micropower Controller: The heart of the device’s ability to retain hot start conditions with minimal background power burn. In this mode, the receiver maintains fine time accuracy from the RTC with periodic satellite calibration, and will decode ephemeris as required. This controller also contains a temperature sensor and can receive interrupts from motion sensors.
  • Smart Sensor Interface: The GSD4t contains a second master-only I²C port for external MEMS sensors, and also supports interrupts from smart sensors for motion detection. This capability augments basic heading and navigation enhancements from simple magnetic compasses to long-term inertial navigation system sources.

GSD4t SiRFHost Software

  • Tracker software resides on the GSD4t chip and generates pseudorange measurements into the SiRFHost navigation engine to compute PVT.
  • SiRFHost and SiRFInstantFix are software packages that reside on the host processor. They provide the navigation solution and ephemeris extension aiding, respectively.
  • SiRFLSM is SiRF premium host software that provides A-GPS support for both user-plane (SUPL) and control-plane (CP) interfaces.

Product details

High-performance Solution

  • High-sensitivity tracking engine to -163dBm
  • Acquisition engine to -160dBm
  • High-performance on-chip LNA, 1.6dB NF
  • SBAS (WAAS or EGNOS)

Low Power

  • 8mW (typical) TricklePower™ at 1Hz update rate
  • Integrated 1.8V to 1.2V switch-mode regulator

Low-risk, High-flexibility Software

  • Boot loadable SRAM: Tracker image downloadable via host port or serial flash
  • SiRFaware technology, including Adaptive Micropower Controller. Retains hot start conditions with only 150μA to 500μA for capture/update
  • Full-sensitivity performance for better coverage
  • Managed auto-refresh for quicker fix times

Tiny Solution Size

  • Single-die 65nm, 42-ball WLCSP, 0.4 mm pitch
  • 3.42 x 2.68 x 0.6mm
  • Single SAW, minimal BOM of 5 to 6 passives

Simple to Use

  • Single 1.8V supply operation
  • Fail-safe I/O, including RTC and TCXO inputs
  • 3.3V compliant integrated TCXO power switch
  • Host I²C, SPI and UART supported